In the field of integrated circuit (IC) technology, an application specific integrated circuit (ASIC) refers to an IC circuit designed and manufactured in accordance with requirements set by the user and by the need for a specific electronic system. A key feature of ASIC is that it is primarily oriented to the needs of a specific user. When compared to a general purpose integrated circuit, it has the advantage of a smaller volume, lower power consumption, higher reliability, higher performance, enhanced privacy, and reduced cost, when mass produced.
FIG. 1 shows an illustrative flow of a conventional ASIC design. In step S101, a gate level netlist is generated. In step S102, a full placement is conducted to determine the physical locations and directions of all the standard gate units and other macros. In step S103, a STA (STA) is performed, preferably using an ideal clock model for clock effect estimation. This is the case because a clock tree has not yet been established by way of establishing a circuit model by extracting parasitics cannot be used to calculate the real arrival time of a clock signal at respective nodes, such that the ideal clock model becomes an approach for computing clock effect of the STA prior to the clock tree being inserted. In step S104, a clock tree is inserted. The clock tree insertion process can be done manually or by an electronic design automation (EDA) tool. For the most popular clock trees, it is preferably accomplished by automatic tools. Its basic principle is to select an appropriate grouping scheme and buffers according to the distance from the respective load timing devices to the clock source. Buffers are placed at a proper location such that the clock skew from the clock source to each load timing device is minimized. The inserted tree-like signal relay network is including buffers is referred to as a clock tree. If the inserted clock tree reaches or is close to the clock effect estimation in the ideal clock model, then the STA result after the clock insertion will be sufficiently close to the analysis result using an ideal clock model. Thus, convergence of timing is maintained and the effect on the design is attained. In step S105, timing analyses with a clock and clock tree adjustments are conducted. In step S106, wiring as well as timing convergence analysis following the wiring is performed. Finally, in step S107, a layout is generated, completing the primary design flow. However, the design flow of the aforementioned FIG. 1 encounters some problems in modern design of very large scale ASIC which are typically embodied in two aspects. In a first aspect, in an ideal clock model, it is always assumed that all the nodes of the same clock tree are to have the same (or very close to) arrival time. However, in a real clock network, this is often very difficult to achieve due to various complicated scenarios. Accordingly, the result obtained from the STA after the clock tree insertion has a noticeable difference with respect to previous ones, resulting in timing convergence failure and design failure. In this case, the ideal clock model often needs to be modified, and the modified model is used to conduct again a full placement, and only then, a clock tree is inserted. The difference between the real clock effect and an ideal clock model is reduced at the cost of increasing the iteration times. Generally, the clock tree insertion itself is time consuming, and such an iterative process further prolong significantly the design turnaround time.
On the other hand, as the scale of ASIC becomes significantly larger, the task of the clock tree insertion itself is increasingly time consuming. For Very Large Scale ASICs (e.g., having ten million gates), if a flatten design is used, the time consumed by the clock tree insertion is often computed in term of days or even weeks. This increases the time of discovering and solving the problems. The problems in both aspects result in excessively long product design period, which may result in losing advantageous market opportunity.
Therefore, there is a need for a method and a system that enables a designer to quickly determine the difference between inserting a clock tree and an ideal clock model as well as changes in the timing analysis results due to that difference, so as to reduce the design time.